Computing devices often employ memory devices including one-time programmable (OTP) memories, which may allow, for example, for firmware or data to be corrected on the computing device post-production. However, OTP memories may be susceptible to bit errors in which one or more bits of the OTP memory “flips” from its correct value to an incorrect value. If left undetected, a bit error may lead to incorrect configuration data being applied to a computing device or an incorrect firmware patch being applied to the computing device, potentially rendering it non-functional.
To provide tolerance against bit errors, computing systems and memories often employ error correction codes to add tolerance to such bit errors, including the correction of single bit errors and the detection of double bit errors. However, as applied to large arrays of data, traditional approaches to generating error correction codes for single bit correction and detection of double bit errors have disadvantages. For example, one traditional approach may be to, for each M-bit word of an N-word array, calculate an error correction code for such word. However, such approach may require a large number of error correction code checkbits. To illustrate, for an array of 16,384 32-bit words, each word would require seven checkbits for single error correction and double error detection, thus requiring 114,688 checkbits for the entire 16,384-word array.
As another example, another traditional approach might be to consider an entire large array of data as an input to an error correction code engine. While this approach may minimize storage overhead for the calculated error correction code (e.g., a 21-bit error correction code for an array of 16,384 32-bit words), it would require an error correction code computation to be performed on all bits of the array at once, which may not be feasible. Also, such approach is not easily scalable to arbitrary arrays of N words of M bits each, especially where N and M are not known ahead of time.